CASTNESS'08 School Abstract

Thursday School Day: 2008 January, 17th

FCM3-SoC Emulation and Fast Prototyping Platform

by Khaled DOUZANE - SCALEO CHIP

[abstract here]

Efficient Design Space Exploration

by Prof. Lothar Thiele - ETH Zurich

Commonly, in the design of multiprocessor embedded systems, the space of possible application configurations that can be mapped onto multiprocessor platforms is huge and the computational effort needed to evaluate all the design solutions is extremely elevated. Finding the “optimal solution” is a key challenge.

We present a fast and precise methodology for multi-objective optimization, under several conflicting criteria. In particular, we will present the frameworks of EXPO (http://www.tik.ee.ethz.ch/expo/expo.html) and PISA (http://www.tik.ee.ethz.ch/sop/pisa/) that together with an analytic performance evaluation method, namely Modular Performance Analysis (MPA), form the basis for design space exploration and mapping optimization of embedded multiprocessor architectures.

Software Stack Generation for MPSoC? Starting from High Level Application Model

by Xavier GUERIN & Alexandre CHUREAU - TIMA Grenoble

In this lesson, we present our application software generation flow and tools starting from a high level application model. This flow and tools are based on the SPIRIT format used to build our intermediate representation. They are able to handle heterogeneous MP-SoC, running multiple software stacks while using different operating systems and communication models. The application software generation tool builds the application’s software stacks by producing optimized and multi-tasked C code and using a flexible operating system and communication programming interfaces management.

Implementation Refinement from High Level Application Model

by Alexandre CHAGOYA-GARZON & Patrice GERIN - TIMA Grenoble

In this lesson, we present a SystemC? -based MPSoC? platform implementation that allows native software simulation while keeping details of the underlying hardware model. The key contribution of this work is a realistic memory mapping modelling that makes possible the simulation and debug of Operating Systems and software applications on complex hardware models with multiple processors and DMA devices. Experimental results with an MJPEG decoder show the efficiency of the proposed method to validate application and OS layers of software on complex hardware architectures.

Tools for ASIP and MPSoC? development

by Stefan Kraemer - RWTH Aachen

With the increasing complexity of MPSoCs? and ASIPs, good tool support is essential in order to guarantee an efficient design flow. For example, micro profiling and instruction set extension (ISE) tools can support the designer in developing an ASIP. Programming heterogeneous MPSoC? is a complex task, therefore, tools are required in order to distribute an application to the different processing elements. An overview of the different tools developed at ISS RWTH-Aachen is given.

Hybrid simulation framework for fast application simulation

by Lei Gao - RWTH Aachen

Instruction set simulation is important for both design space exploration and platform-dependent software development. It is desired to have high simulation speed as well as good accuracy. To address this problem, we propose a hybrid simulation framework, in which a novel Virtual CoProcessor? (VCP) is introduced to facilitate fast application simulation.

Dissection of a high-performance audio application on a RISC + floating-point VLIW DSP MPSOC: Diopsis 940

by Stefano FASCIANI - ATMEL Roma

[abstract here]

Friday School Day: 2008 January, 18th

DNP: a 3D Torus interconnect for Shapes platform

by Davide ROSSETTI -INFN (Istituto Nazionale Fisica Nucleare) Roma

Efficiently scaling a multi-processor parallel computer to hundreds or thousands of processing nodes is a challenge. In this lesson we briefly introduce the 3D Torus network, considering its pros and cons. Next, we introduce the Distributed Network Processor (DNP) developed in the framework of the Shapes project. Finally we describe the DNP HW structure and discuss its proposed programming APIs.

Zebu: a compiler framework for MPSoCs? architectures

by Fabrizio Ferrandi - Politecnico di Milano

This class presents a design toolchain for automatic transformation of sequential C source code into parallel one. Parallelism in the produced code is expressed by annotating produced code with OpenMP? pragmas. This class will shows how a slightly modified version of GNU/GCC 4.3 compiler is used to parse and analyze the input C code. Then it is described how a Program Dependence Graph with Feedback Edges (FPDG) is produced starting from the information extracted by GCC: after some optimizations and further analysis this graph is partitioned into groups of operations. Each group represents potential task. At the end, after that further transformations to the identified groups are performed to produce a fork-join compliant task graph, the OpenMP? annotated C source code can be produced. The task partitioning toolchain is currently under developement in the hArtes European project.

Optimizing task and data representations

by Tim TODMAN - Imperial college - London

[abstract here]

Codesign for heterogeneous systems

by Yuet Ming LAM - Imperial College - London

[abstract here]

Implementing DSP Algorithms in NU-Tech for Real Time Applications

by Ariano LATTANZI - LEAFF/UNIPVM

[abstract here]

Wave Field Synthesis - from Theory to Implementation

by Michael BECKINGER - FRAUNHOFER IDMT

In this lesson, we present the flow path from theory of wave field synthesis (WFS) sound reproduction systems to real DSP implementation with several examples. The presentation gives an overview on WFS theory. Then the WFS signal processing software development workflow for multi processor/multi DSP platforms will be shown from a programmer's perspective. Several programming aspects (e.g. real-time and low latency) for multi processor programming, some implementations on multiprocessor systems and planned implementations within the SHAPES project will be presented.

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