CASTNESS'08 15-18 January 2008 - ROMA - Italy

Computing Architectures and Software Tools for Numerical Embedded Scalable Systems

Please find here the presentations delivered during CASTNESS'08

shApes project: scalable software hardware architecture platform for embedded systems

• SHAPES_HW_Paolucci_CASTNESS08.ppt: Pier Stanislao Paolucci - updates about the shApes multi-processor tiled hardware architecture
• SW_Architecture_Overview.ppt: L. Thiele - shApes; software architecture overview
• SHAPES-Applications.pdf: T. Sporer - shApes: applications overview
• RL-castness-2008.ppt: R. Leupers - VSP: virtual shApes platform
• 15-01-2008-DOL-Castness-Iuliana.ppt: I. Bacivarov - shApes DOL: distributed operation layer
• Talk_Fred_Rousseau_TIMA.pdf: F. Rousseau - shApes: overview of the software stack generation starting fom high level application model
• Goossens-Castness-Workshop-080115.ppt: G. Goossens - ShApes? - generation of Efficient SDK for VLIW-DSPs
• Castness08_THALES_dr_v3.ppt: D. Ragot - shApes - real-time support for heterogeneous SoC?
• coppola.ppt: M. Coppola - shApes - Spidergon sTNoC: the communication infrastructure fro multiprocessor architectures
• DesignSpaceExploration.pdf: L. Thiele - Efficient design space exploration
• CASTNESS_08_GUERIN_CHUREAU_FINAL.pdf: X. Guerin, A. Chureau - Software stack generation for MPSoC? starting from high level application model
• CASTNESS_08_CHAGOYA_GERIN_FINAL.pdf: A. Chagoya-Garzon, P. Gerin - Implementation refinement from high level application model
• SKR_castness_2008.pdf: S. Kraemer - Tools for ASIP and MPSoC? development
• Castness2008_LeiGao.pdf: L. Gao - Hybrid simulation approach for application simulation
• shapes-WFS-theory-to-implementation_final.pdf: M. Beckinger - WFS (Wave Field Synthesis): from theory to implementation
• Goossens-Castness-School-080117.ppt: G. Goossens - Ultra-low power? Think Multi-ASIP Soc
• castness08-dnp.pdf: D. Rossetti - ShApes? DNP (Distributed Network Processor)

hArtes project: holistic approach to real time embedded systems*

• hArtes_Introduction.ppt: hArtes_Introduction.ppt
• CASTNESS_hArtes_Toolchain_-v1.ppt: K. Bertels - hArtes: software architecture overview
• hArtes_SW_partitioning.ppt: F. Ferrandi - hArtes; software partitioning overview
• castness-luk5.ppt: W. Luk - hArtes: exploring and optimising reconfigurable designs
• HARTES_Application_Overview_V1.ppt: F. Piazza - hArtes: application overview
• In-Car_audio_Application_v1.ppt: F. Piazza - hArtes: in-car audio applications
• castness2008hardPlatform.pdf: r. Tripiccione - hArtes: hardware application overview
• Scaleo_CASTNESS_FCM_B22.ppt: K. Douzane - FCM3-SoC emulation and fast prototyping platform
• castness-final.ppt: A. Tumeo - Zebu: a compiler framework for MPSoc architectures
• Imperial-todman-transformations-castness08.ppt: T. Todman - Optimizing task and data representations
• Imperial-Lam-codesign-castness08.ppt: Y. M. Lam - Codesign for heterogeneous systems

SARC project: scalable computer architecture

• SARC_overview.ppt: G. N. Gaydadjiev - Some more general overview about SARC
• castness08-SARC_Achitecture.ppt: A. Ramirez - The SARC architecture
• castness08-SARC-PM-XavierMartorell.pdf: X. Martorell - The SARC Programming model

AETHER project: Self-adaptive embedded technologies for pervasive computing architectures

• 080116--AETHER_Overview_CASTNESS.ppt: c. Gamrat - AETHER: from reconfigurable to self-adaptive computing
• AETHER_CASTNESS_ITIV_v3.ppt: K. Paulsson - AETHER: Self-adaptive implementation using dynamically reconfigurable hardware
• AETHER_OE_0108.ppt: J. P. Diguet - The AETHER operating environment

MORPHEUS project: Multi-purpose dynamically reconfigurable platform for intensive heterogeneous processing

• Castness-Morpheus.ppt: P. Bonnot - Morpheus overview

Special session on Advanced Embedded Audio Applications

• 20080116_Additive_Musical_Synthesis.ppt: L. Seno, P. Bazzana - Additive Musical Synthesis
• OmologoCastness08.pdf: M. Omologo - Acoustic scene analysis and distant talking speech recognition for smart home
• WFS-Theory-Applications-Market.pdf: T. Sporer - WFS: Wave Field Synthesis - theory, applications and market

Seventh Research Framework Programme (FP7)

• FET_CASTNESS08.ppt: J. M. Auger - FET Research on Massive ICT Systems
• Tsarchopoulos_CASTNESS-2008_presentation.ppt: P. Tsarchopoulos - Computing systems in FP7: call-1 results and future outlook

PROGRAM

WORKSHOP	first day					start	end
Tuesday 15 Jan 2008			registration		01.00	08.00	09.00
	WELCOME		speaker name	welcome	0.05	09.00	09.05
	CASTNESS'08 AGENDA		Pier Stanislao PAOLUCCI	ATMEL and INFN	00.10	09.05	09.15
	HARTES: Holistic Approach to Real Time Embedded Systems	overview	Piergiovanni BAZZANA	ATMEL Roma, IT	00.20	09.15	09.35
	HARTES	sw architecture overview	Koen BERTELS	TU Delft, NL	00.20	09.35	09.55
short break					00.15	09.55	10.10
	HARTES	sw partitioning overview	Fabrizio FERRANDI	Politecnico di Milano, IT	00.20	10.10	10.30
	HARTES	Exploring and optimising reconfigurable designs	Wayne LUK	Imperial College London, UK	00.20	10.30	10.50
	HARTES	application overview	Francesco PIAZZA	Università Politecnica delle Marche, IT	00.20	10.50	11.10
coffee break					0.30	11.10	11.40
	HARTES	in-car audio algorithms	Francesco PIAZZA	Università Politecnica delle Marche, IT	00.20	11.40	12.00
	HARTES	hw application platform	Raffaele TRIPICCIONE	Università di Ferrara, IT	00.20	12.00	12.20
lunch					01.20	12.20	13.40
	SHAPES: Scalable SW and HW Architecture Platform for Embedded Systems	multi-tiled HW architecture overview	Pier Stanislao PAOLUCCI	ATMEL Roma and INFN Roma, IT	00.20	13.40	14.00
	SHAPES	sw architecture overview	Lothar THIELE	EHTZ-Zurich, CH	00.20	14.00	14.20
	SHAPES	applications overview	Thomas SPORER	FRAUNHOFER IDMT	0.20	14.20	14.40
short break					00.15	14.40	14.55
	SHAPES	VSP - Virtual Shapes Platform	Rainer LEUPERS	RWTH AACHEN, D	00.20	14.55	15.15
	SHAPES	DOL - Distributed Operation Layer	Iuliana BACIVAROV	ETHZ-Zurich, CH	00.20	15.15	15.35
	SHAPES	Overview of the Software Stack Generation Starting from High Level Application Model	Frederic ROUSSEAU	TIMA, FR	00.20	15.35	15.55
coffee break					00.30	15.55	16.25
	SHAPES	CHESS C Compiler for shapes	Gert GOOSSENS	TARGET Compiler Technology, B	00.20	16.25	16.45
	SHAPES	Real-Time support for Heterogeneous SoC?	Dominique RAGOT	THALES, FR	00.20	16.45	17.05
	SHAPES	Spidergon STNoC? : the communication infrastructure for Multiprocessor architectures	Marcello COPPOLA	ST Microelectronics, FR	00.20	17.05	17.25
	SHAPES	DNP - Shapes Distributed Network Processor	Piero VICINI	INFN	00.20	17.25	17.45
WORKSHOP	second day					start	end
Wednesday 16 Jan 2008
	SARC	Some more general overview about SARC	Georgi N. GAYDADJIEV	TU Delft, NL	00:20	09:00	09:20
	SARC	The SARC architecture	Alex RAMIREZ	Universitat Politècnica de Catalunya/BSC, ES	00:20	09:20	09:40
	SARC	The SARC programming model	Xavier MARTORELL	Universitat Politècnica de Catalunya/BSC	00:20	09:40	10:00
short break					00:15	10:00	10:15
	AETHER	From Reconfigurable to Self-Adaptive computing	Christian GAMRAT	CEA LIST	00:20	10:15	10:35
	AETHER	Self-Adaptive Implementation using dynamically reconfigurable hardware	Katarina PAULSSON	U. KARLSRUHE	00:20	10:35	10:55
	AETHER	An operating environment for self-adaptive computing elements	Jean-Philippe DIGUET	U. BRETAGNE SUD	00:20	10:55	11:15
coffee break					00:30	11:15	11:45
	MORPHEUS	overview	Philippe BONNOT	THALES	00:20	11:45	12:05
	Invited talk	Programming Heterogeneous MPSoC? Architectures	Ahmed JERRAYA	CEA LETI	00:20	12:05	12:25
	SHAPES	DEMO of programming/simulation environment on Multi-loudspeaker WFS			00:15	12:25	12: 40
lunch					01:00	12:40	13:40
	Invited talk	Additive Musical Synthesis	Lorenzo SENO & Piergiovanni BAZZANA	CRM & ATMEL	00:20	13:40	14:00
	Invited talk	Acoustic scene analysis and distant-talking speech recognition for smart home	Maurizio OMOLOGO	FBK-IRST	00:40	14:00	14:40
short break					00:15	14:40	14:55
	Invited talk	Wave Field Synthesis - Theory, Applications and Market	Thomas SPORER	FRAUNHOFER IDMT	00:40	14:55	15:35
		Research on massive ICT systems	Jean-Marie AUGER	European Commission	00:20	15:35	15:55
		Computing Systems in FP7: Call-1 results and future outlook	Panagiotis TSARCHOPOULOS	European Commission	00:20	15:55	16:15
coffee break					00:30	16:15	16:45
	BRAINSTORMING SESSION	panel + feedback of all participants	Key issues in embedded systems for advanced audio, RISC + DSP vs general purpose tiles, floating-point vs fixed point, time coherence (sampling, processing), real-time os vs small-footprint os, quality and cost of microphone and loudspeaker arrays, …”	cross fertilization round table	00:45	16:45	17:30
	Invited talk	The FCM (Fast Configurable MicroChip? ) and easySoc concept	Khaled DOUZANE	SCALEO CHIP	00:20	17:30	17:50

SCHOOL	third day					start	end
Thursday 17 Jan 2008						09:00
	FCM3-SoC Emulation and Fast Prototyping Platform		Khaled DOUZANE	SCALEO Chip	00:45	09:00	09:45
short break					00:15	09:45	10:00
	Efficient Design Space Exploration		Lothar Thiele	ETH-Zurich	00:45	10:00	10:45
coffe break					00:30	10:45	11:15
	Software Stack Generation for MPSoC? Starting from High Level Application Model		Xavier GUERIN & Alexandre CHUREAU	TIMA	00:45	11:15	12:00
short break					00:15	12:00	12:15
	Implementation Refinement from High Level Application Model		Alexandre CHAGOYA-GARZON & Patrice GERIN	TIMA	00:45	12:15	13:00
lunch					01:00	13:00	14:00
	Tools for ASIP and MPSoC? development		Stefan KRAEMER	RWTH-AACHEN	00:45	14:00	14:45
short break					00:15	14:45	15:00
	Hybrid simulation framework for fast application simulation		Lei GAO	RWTH-AACHEN	00:45	15:00	15:45
short break					00:15	15:45	16:00
	Wave Field Synthesis		Michael BECKINGER	FRAUNHOFER IDMT	00:45	16:00	16:45
coffe break					00:30	16:45	17:15
	Chess Retargetable Compiler		Gert GOOSSENS	TARGET Compiler Technology	00:45	17:15	18:00

SCHOOL	fourth day					start	end
Friday 18 Jan 2008						10:00
	Distributed Network Processor		Davide ROSSETTI	INFN	00:45	10:00	10:45
coffee break					00:30	10:45	11:15
	Zebu: a compiler framework for MPSoCs? architectures - I		Fabrizio FERRANDI	POLIMI	00:45	11:15	12:00
short break					00:15	12:00	12:15
	Zebu: a compiler framework for MPSoCs? architectures- II		Fabrizio FERRANDI	POLIMI	00:45	12:15	13:00
lunch					01:00	13:00	14:00
	Optimizing task and data representations		Tim TODMAN	IMPERIAL	00:45	14:00	14:45
short break					00:15	14:45	15:00
	Codesign for heterogeneous systems		Yuet Ming LAM	IMPERIAL	00:45	15:00	15:45
short break					00:15	15:45	16:00
	Implementing DSP Algorithms in NU-Tech for Real Time Applications		Ariano LATTANZI	LEAFF	00:45	16:00	16:45
coffee break					00:30	16:45	17:15
	Dissection of a high-perf. audio application on a RISC + floating-point VLIW DSP MPSOC: Diopsis 940		Stefano FASCIANI	ATMEL	00:45	17:15	18:00

planned duration of short talks, lessons and breaks

talkanddisc		0.20
lessonanddisc		0.45
shortbreak		0.15
coffeebreak		0.30
lunchbreak		1.00

please fill CastNess08SchoolAbstracts with the abstracts of the school lessons.

WORKSHOP AND SCHOOL FORMAT - 4 days total

The first 2 days (CASTNESS WORKSHOP) are composed of 20 minute talks from senior academic and industrial researchers and european/national research officers.

Starting from the third day the (CASTNESS SCHOOL) hosts in depth lessons about current research activities on exploration/generation tools of system sw and hw. The lessons of the school will be delivered by senior or brilliant junior academic and industrial researchers.

NOTE This second edition focus on the architecture of HW and System SW, plus first demo sessions, plus first application feedback.

Programme Committee

The programme committe is composed of SHAPES and HARTES members.

• SHAPES: Ahmed Jerraya, Rainer Leupers, Pier Stanislao Paolucci, Frederic Rousseau, Lothar Thiele, Piero Vicini.
• HARTES: Piergiovanni Bazzana, Volker Hahn, Wayne Luk, Francesco Piazza, Remond Sautreau, Donatella Sciuto.

Local Organizing Committee

Eugenio Faggioli, Gigliola Gori, Marisa Iannarelli, Roberto Marega, Pier Stanislao Paolucci, Mersia Perra, Piero Vicini.

CASTNESS'08 OBJECTIVE

The objective is cross-dissemination among european projects: SHAPES, HARTES, SARC, AETHER, MORPHEUS, the APE Massive Parallel Processor initiative, and the academic and industrial research community sharing the topics addressed by those project. The community addressed by ARTIST2, HIPEAC and ARTEMIS are warmly welcome.

CASTNESS'08 is a dissemination event promoted by SHAPES www.shapes-p.org and HARTES www.hartes.org European Integrated Projects.

CASTNESS08 SOCIAL DINNER, 15th evening

In a nice atmosphere, you could exchange impression about the event, the topics discussed or maybe just simply relax at the social dinner, enjoying good food and wine.

The social dinner will cost ~*40Euro/p to be payed (cash)at the CASTNESS registration*, the 15th in the morning.

After payment you will receive a voucher, and at the restaurant you will get a receipt at your name and, of course, your dinner!

If you would like to be part of the social dinner, we would appreciate if you could send us a confirmation at infocastness@roma1.infn.it.

Proceed herefrom to CastNess08Registration, CastNess08ParticipantList, CastNess08Hotels, CastNess08Location, CastNessRomaMaps, CastNess08SchoolAbstracts, CastNess08Pictures? , CastNess08MailingLists, CastNess08ParallelMeetingSessions.

Proceed herefrom to

• CastNess08Registration,
• CastNess08Hotels,
• CastNess08Location,
• CastNessRomaMaps,
• CastNess08ParticipantList
• CastNess08ParallelMeetingSessions
• Castness08BrainstormingSession
• Castness08SocialDinner